Two-Input NOR Gate

Fabrication process

Fabrication process of an integrated circuits involves many technical aspects. Most of the technical aspects related to the functionality and the physical size of the chip. The fabrication process of an integrated IC constitutes first the determination of the amount of current, voltage and the resistance associated with the circuit. Thereafter the size of the different elements that can be incorporated in the design of the IC is determined. The size is normally specified in terms of the dimensions of the doping agents as well as the substrate (Yu and Tan, n.d.).

The wafer is first prepared from the basic understanding of the circuit. For instance, the development of a two-input NOR gate involves the determination of the total amount of resistance that can be associated with the driver and the load circuits. Thereafter the physical dimensions of the contacts, the driver circuit, the gate circuit and the source circuit are determined. At this point the amount of doping agent and the shape of the doping is determined. The resistivity of the material selected as the doping agent determines the shape and the size of the material to be implanted (Yu and Tan, n.d.).

The following figure can be used to illustrate the general layout of the circuit that is used to build a two-input C-mos NOR gate.

Figure 1 Circuit diagram of a two-input NOR gate

As can be seen from the above diagram the circuit consists of a parallel connected n-net and a series connected complementary p-net. The input voltages are applied to the gates of the p and n MOS transistors. When either both or one of the inputs is set to be high there is a creation of a conducting path between the ground and the output. In this case the p-net is cut-off. For a case where both the input voltages are set to low the n-net is cut off and the p-net creates a conducting path between the supply voltage and the output node. As such, the complementary circuit behaves in such a way as if it is either connected to the ground or supply voltage (Tiku and Biswas, n.d.). The switching threshold voltage for the circuit can be expressed as shown below;

It can further be noted that the realization of the above circuit can easily be analyzed from the amount of current, resistance and potential difference that drives the circuit (Tiku and Biswas, n.d.). The physical size and dimensions of the contacts of the gate together with the dimensions of the two transistors can be computed as shown below;

To start with the computation the following parameters have already been supplied for the circuit;

  • Minimum feature size λm = 0.2μm
  • Supply voltage VDD=5v (logic1 input)
  • Threshold voltage VT= 0.25 v
  • Maximum alignment error=1μm
  • Oxide Capacitance Co = 5×10-4 Fm2
  • Electron mobility 1 m2V-1s-1
  • Hole mobility 05 m2V-1s-1

Assuming sheet resistance is 100ohm/square,

RL = R (sheet).NL = 100*15 = 1500 ohms

l =

Inserting the values in the above expression we realize;

RL =18 RB

Note also that NL=L/W

Hence 10W=L

On the side of the driver circuit, the following parameters can as well be computed;

RL = R (sheet).NL = 100*0.5 = 50 ohms

l =

Inserting the values in the above expression we realize;


Note also that NL=L/W


R=100 L/W



However, VDD is 5.0V. Hence IDS can be computed as given below;


=1.8*10-4/2 [W/L]{5-2}2



R=100 L/W


R2 =5*1.78*10-4*100R

R=500 ohm

Hence L=2W

From the above computations the following circuit layout and the physical dimensions were derived accordingly;



As can be seen from the above circuit the realization of the physical layout has been drawn on a scale of 1:0.2. The contacts of the IC together with the gate and the drain circuit have been illustrated in the above figure. The source circuit together with the physical dimensions have been illustrated as part of the implanted and doped materials. The above layout therefore serves as the main building block for the circuit and in turn the IC. The electrical properties for the desired doping agents can then be decided at this stage before the final fabrication process. Additionally, the shape of the circuit is also noted in form of the small squares that are defined by the minimum feature size. Most of the shapes that are designed for the IC take a rectangular or square shapes in order to accurately determine the parameters of the circuit (Tiku and Biswas, n.d.).


The paper has determined the relevant circuit parameters for the two-input NOR gate. The paper has also computed the physical dimensions of the circuit layout in terms of the length and width of the wafers. The dimensions of the circuit were determined in terms of the minimum feature size which was already defined for the materials to be in the design. The physical realization of the circuit was demonstrated in a diagram drawn to scale. Both the contacts, the source, drain and the gate layout were illustrated and drawn to scale.



Tiku, S. and Biswas, D. (n.d.). III-V integrated circuit fabrication technology. 1st ed.

Yu, H. and Tan, C. (n.d.). Advances in 3D integrated circuits and systems. 1st ed.




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